1. Field of the Invention
The present invention relates to a duty detection circuit capable of generating a duty detection signal with high frequency, and a clock generation circuit including the same. The present invention also relates to a semiconductor device including the clock generation circuit.
2. Description of Related Art
In recent years, a synchronous memory that operates synchronously with a clock has been widely used as a main memory of personal computers or the like. Particularly in a DDR (Double Date Rate) synchronous memory, it is necessary to accurately synchronize input/output data with an external clock. Therefore, a DLL (Delay Locked Loop) circuit that generates an internal clock synchronous with the external clock is employed.
A DLL circuit of a certain type adjusts a rising edge of an internal clock based on a result of phase comparison, and adjusts a falling edge of the internal clock based on a result of duty detection. According to this method, it is possible to generate an internal clock coincident with an external clock in phase, and to adjust a duty ratio of the internal clock to approximately 50% even when a duty ratio of the external clock is offset from 50%.
To detect the duty ratio of the internal clock, a duty detection circuit is used (see Japanese Patent Application. Laid-open No. 2006-217223). The duty detection circuit includes an integral capacitor into or from which electricity is charged or discharged synchronously with an internal clock, and determines a duty ratio of the internal clock based on a voltage of the integral capacitor. Accordingly, to perform a duty detection operation, it is necessary to perform charging and discharging operations over cycles that are integral multiples of the internal clock. Besides, it is necessary to perform an operation for determining a voltage of an integral capacitor and a latch operation for a determination result. Accordingly, a plurality of cycles are required for a series of operations.
By way of example, when two cycles are necessary for charging and discharging operations, one cycle is necessary for determining the voltage of the integral capacitor, and one cycle is necessary for the latch operation for the determination result, four cycles are necessary in all to complete a series of operations. That is, in this case, an update frequency of the duty detection signal is limited to four cycles and the duty detection signal cannot be updated in shorter cycles than the four cycles.
Nevertheless, there has been a demand of updating duty detection signals more frequently.
For example, in a case of a DLL circuit of a type to adjust the rising edge of the internal clock based on the result of the phase comparison, and to adjust the falling edge of the internal clock based on the result of the duty detection as described above, it is necessary to perform the duty detection operation after adjusting the rising edge of the internal clock. When it is necessary to use, for example, eight cycles to adjust the rising edge of the internal clock, a control period of the DLL circuit is 12 cycles at the shortest as long as the generation frequency of generating the duty detection signal is four cycles.
Furthermore, when nine cycles are necessary to adjust the rising edge of the internal clock, then a correct duty detection signal cannot be obtained promptly in the ninth cycle, and it is the 12th cycle when the duty detection signal is updated next to the eighth cycle. Therefore, the control period of the DLL circuit is 16 cycles and the control period is considerably increased.
Moreover, when jitter is to be suppressed by using duty detection signals obtained over a plurality of periods, it disadvantageously takes a very long time for determination. For example, when a duty adjustment direction is determined based on the five duty detection signals and the generation frequency of the duty detection signal is four cycles, it takes 20 cycles of time to make the duty determination alone.